#论文/研究

Camera pose matters for video understanding! Today's MLLMs excel at recognizing activities, but still struggle with the underlying space and ego/object dynamics in video. We trace this gap to a missing piece: camera pose. Introducing Cambrian-P: a multimodal LLM natively grounded in camera pose. (1/n)

好奇我们万亿级智能体基础模型背后的秘密武器吗？它来了！🥳 去年，我们发布了 IcePop，通过双边掩码来稳定 MoE RL。随着我们深入探索，意想不到的事情发生了：掩码比例下降了，而训练-推理不匹配却持续增长！😞 今年，我们推出 𝑲𝑷𝒐𝒑🪩，它用二元 KL 散度取代固定比例约束，自适应地掩码不合适的 token！掩码比例会随训练过程中训练-推理差距的波动而自适应调整，从而在长时程智能体 RL rollout 中保持策略优化稳定且有效。 通过这一简单改动，它使我们的 Ring-2.6-1T 在纯 RL 训练下于 SWE-bench-Verified 上取得超过 76 的成绩！ 无需修改基础设施。无需 routing replay。只需一个参数，用 𝑲𝑷𝒐𝒑 为你的智能体 RL 赋能！ 点击了解更多细节！ 📜Blog: https://ringtech.notion.site/kpop

好奇我们万亿级智能体基础模型背后的秘密武器吗？它来了！🥳 去年，我们发布了 IcePop，通过双边掩码来稳定 MoE RL。随着我们深入探索，意想不到的事情发生了：掩码比例下降了，而训练-推理不匹配却持续增长！😞 今年，我们推出 𝑲𝑷𝒐𝒑🪩，它用二元 KL 散度取代固定比例约束，自适应地掩码不合适的 token！掩码比例会随训练过程中训练-推理差距的波动而自适应调整，从而在长时程智能体 RL rollout 中保持策略优化稳定且有效。 通过这一简单改动，它使我们的 Ring-2.6-1T 在纯 RL 训练下于 SWE-bench-Verified 上取得超过 76 的成绩！ 无需修改基础设施。无需 routing replay。只需一个参数，用 𝑲𝑷𝒐𝒑 为你的智能体 RL 赋能！ 点击了解更多细节！ 📜Blog: https://ringtech.notion.site/kpop

🇨🇳 Huawei reveals a new chip design breakthrough under US sanctions pressure. A design approach meant to close the gap with TSMC and Intel without relying only on smaller transistors, by making chip signals travel less distance. They want 1.4nm-class density without owning the world’s best lithography tools i.e. they are trying to replace Moore’s Law with Tau Scaling Law. To note, Huawei has been blocked from normal access to TSMC since the US tightened foreign direct product rules around Huawei in 2020, and TSMC later said it had not supplied Huawei since mid-September 2020. Proposed τ Scaling as a new way to make chips faster when shrinking transistors is no longer delivering the same gains. Said its next Kirin phone chip will be the first full test of Tau Scaling Law, Old chip progress mostly came from making every transistor smaller, but Huawei’s idea shifts the target from smaller geometry to shorter signal delay, meaning less time wasted while electrical signals crawl through wires, gates, memory paths, and system links. LogicFolding attacks the circuit layout itself by folding logic blocks closer together, shortening critical wires, reducing resistance and parasitic capacitance, and letting signals switch faster with denser placement. So LogicFolding is the circuit-level piece: it tries to place related logic closer together, shorten key wires, cut electrical drag from resistance and parasitic capacitance, and raise performance without needing a full manufacturing-node leap. Huawei is also pushing the same timing idea across the full stack: transistors, circuits, chip architecture, software scheduling, and system interconnects all get tuned to reduce τ, the delay constant that limits speed and efficiency. The bold claim is that Huawei has already mass-produced 381 chips using this thinking, and future high-end chips could reach density comparable to 14Å, or 1.4nm, without relying only on classic process shrinkage. Says this path could reach 1.4nm-class, or 14Å-class, density by 2031, while TSMC and Intel target similar physical nodes around 2029. Huawei calls it Her’s Law, after He Tingbo, the chip leader who helped turn HiSilicon into Huawei’s survival engine after US export controls. --- huawei. com/en/news/2026/5/ieee-iscas-tau-scaling

In Oct last year, Representation Autoencoders provided an elegant solution to unified tokenization for understanding and generation. Today we make them a bit more simple. a bit more general. Result: >10x faster convergence, better reconstruction, better generation. And yes we test them on T2I and world models :) Introducing RAEv2

A breakthrough by OpenAI in a very famous Combinatorics problem, the Planar Unit Distance problem by Erdos 1946. The problem is amazing because it can be described to a first-grader: Find a way to place n points on the plane to maximize the number of pairs that have distance exactly 1. For example, if you have n=4 points on a square (of side-length 1) you have 4 pairs of distance 1. The diagonals have length sqrt(2) so don't count. But you can squeeze one diagonal and create a point-set with n=4 points and 5 pairs of distance 1. And you can't get more than 5 pairs from n=4 points, so we are done with n=4 points. Now, if you place n points on a line, you have n-1 pairs of distance 1. In general, all known constructions of n points had a number of pairs scaling essentially linearly: n^{1+something vanishing} It seems that the model found a way to place n points on the plane so that their unit distances scale super-linearly: like n^{1+delta} for some *constant* delta. Delta was not explicitly specified apparently, but a forthcoming refinement by Will Sawin shows delta=0.014 works, according to the announcement. This is incredible progress for mathematics, since this is (unlike previous Erdos problems solved by AI) a major breakthrough, in one of the most studied problems in combinatorial geometry. If you're in mathematics research now, you feel the AGI. Lijie Chen said it honestly in the video: "It's very hard to sleep, man"

Today, we share a breakthrough on the planar unit distance problem, a famous open question first posed by Paul Erdős in 1946. For nearly 80 years, mathematicians believed the best possible solutions looked roughly like square grids. An OpenAI model has now disproved that belief, discovering an entirely new family of constructions that performs better. This marks the first time AI has autonomously solved a prominent open problem central to a field of mathematics.